1. Field of the Invention
The present invention relates to a circuit for controlling the reading, erasure, addressing and other management modes of memory words in a memory system. A mode of management is defined for each memory word by a special memory word called a descriptor. Each descriptor defines a management mode for a memory zone that includes a plurality of memory words. The invention can be used to manage memory systems including non-volatile memories such as electrically erasable and programmable memories (EEPROMs), and unerasable electrically programmable memories (EPROMs).
2. Discussion of the Related Art
There are known memory partitions, notably in chip card type applications, wherein non-volatile memory is distributed into zones in which only reading can be done, zones where reading and writing can be done, zones where only reading and erasing can be done, zones where not even reading can be done (notably when secret codes of the card are involved), and so on. Typically, the operating system of a chip card such as this, in electronic integrated circuits, comprises a microcontroller that permits only the authorized functions to be performed within each memory zone, as a function of a protection configuration defined by a descriptor corresponding to the memory zone.
An arrangement is known in which the memory zones that can be used in reading, writing or erasure are contiguous with one another and are arranged in one part of the memory, while the zone descriptors corresponding to these memory zones are arranged in another part of the memory. The reference to differing parts of the memory is both physical (the memory cells are arranged at different geographical locations on the memory map) and functional (the addresses of the different zones correspond to significant address bits equal to 0 for one part and to 1 for the other part).
A descriptor is a word of the memory that comprises a first group of bits that can be used to define the protection of the memory zone, and another group of bits marking the boundaries of the zone in the memory. These boundaries are constituted by start-of-zone and end-of-zone addresses. In the above-described system, a zone descriptor includes a single boundary address, i.e., the address of the end of the zone corresponding to this descriptor. The address of the start of the zone corresponding to a descriptor is the address, plus one unit, of the last memory word of the previous zone.
A system such as this works well but has a drawback in that, notably in applications with bank type chip cards, the addressing of the words of the memory is sequential. Thus, the access to a desired memory word cannot be obtained by using an address counter until the counter has inspected all the addresses of the words that precede the desired word, starting from the original address of the memory (00 . . . 00). To have access subsequently to another word of the memory, it is normally necessary, after having made the counter count up to the last address of the memory, to make it start counting again up to the address of this next desired word. It is also possible, in certain cases, to prompt a zero-setting of the counter before counting again up to the address of the next desired word. However, the mode of management or protection of the next desired word may be different from the mode of management of the previously accessed word. This complicates the concomitant handling, with this counter, of the modes of protection to be followed. It is possible, for example, to resolve the problem by limiting the excursion of the counter within a chosen counting window. However, this complicates the circuit and furthermore reduces the flexibility of use.
One object of the invention is to provide a simplified addressing device that can be used when it is sequential, even though the sequential character of this addressing with this counter is not completely indispensable. For illustrative purposes, an addressing scheme is described that is done word by word in the memory, each word being located in a different row of the memory. Within each word, addressing is done bit by bit. For a given word, a column decoder enables the connection, successively, of each of the bit lines of the word bit (the columns) to a single reading circuit, while a row decoder makes it possible, after the reading of a word, to go to the reading of the next word in a following row.